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Datasheet, V2.0, 15 May 2003
PWM-FF IC
ICE3DS01L ICE3DS01LG
Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell
Power Management & Supply
Never
stop
thinking.
ICE3DSO1L(G) Revision History: Previous Version: Page Subjects (major changes since last revision) 2003-05-15 Datasheet
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Edition 2003-05-15 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
(c) Infineon Technologies AG 1999. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
F3
Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell
Product Highlights
P-DIP-8-6
* Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Latched Off Mode to increase Robustness and Safety of the System * Adjustable Blanking Window for High Load Jumps to increase Reliability Features
* * * * * * * * * * * * * * * Active Burst Mode for lowest Standby Power @ light load controlled by Feedback Signal Fast Load Jump Response in Active Burst Mode 500V Startup Cell switched off after Start Up 110kHz internally fixed Switching Frequency Latched Off Mode for Overtemperature Detection Latched Off Mode for Overvoltage Detection Latched Off Mode for Short Winding Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode for VCC Undervoltage User defined Soft Start Minimum of external Components required Max Duty Cycle 72% Overall Tolerance of Current Limiting < 5% Internal Leading Edge Blanking Soft Switching for Low EMI
test
ICE3DS01L ICE3DS01LG
P-DSO-8-8
Description
The F3 Controller provides Active Burst Mode to reach the lowest Standby Power Requirements <100mW at no load. As during Active Burst Mode the controller is always active there is an immediate response on load jumps possible without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore Latched Off Mode is entered in case of Overtemperature, Overvoltage or Short Winding. If Latched Off Mode is entered only the disconnection from the main line can reset the Controller. Auto Restart Mode is entered in case of failure modes like open loop or overload. By means of the internal precise peak current limitation the dimension of the transformer and the secondary diode can be lower which leads to more cost efficiency. An adjustable blanking window prevents the IC from entering Auto Restart Mode or Active Burst Mode in case of high Load Jumps.
Typical Application
+
85 ... 270 VAC
CBulk
CVCC
Snubber
Converter DC Output
-
HV
Startup Cell
VCC
PWM Controller Current Mode
Gate
Precise Low Tolerance Peak Current Limitation
Power Management
CS
RSense
Control Unit
Active Burst Mode
FB
SoftS
CSoftS
GND
Latched Off Mode
Auto Restart Mode
ICE3DS01/G
Type ICE3DS01L ICE3DS01LG
Ordering Code ES Samples available Q67040-S4549-A102
FOSC 110kHz 110kHz
Package P-DIP-8-6 P-DSO-8-8
Version 2.0
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F3 ICE3DS01L/LG
Table of Contents 1 1.1 1.2 1.3 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.3 3.6.3.1 3.6.3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5 6 Page
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration with P-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration with P-DSO-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
Pin Configuration and Functionality
Pin Configuration with P-DIP-8-6
Symbol SoftS FB CS HV HV Gate VCC GND Function Soft-Start Feedback Current Sense High Voltage Input High Voltage Input Driver Stage Output Controller Supply Voltage Controller Ground
1.2
Pin 1 2 3 4 5 6 7 8
Pin Configuration with P-DSO-8-8
Symbol SoftS FB CS Gate HV N.C. VCC GND Function Soft-Start Feedback Current Sense Driver Stage Output High Voltage Input Not connected Controller Supply Voltage Controller Ground
Package P-DIP-8-6
Package P-DSO-8-8
SoftS
1
8
GND
SoftS
1
8
GND
FB
2
7
VCC
FB
2
7
VCC
CS
3
6
Gate
CS
3
6
N.C.
HV
4
5
HV
Gate
4
5
HV
Figure 1 Note:
Pin Configuration P-DIP-8-6(top view) Pin 4 and 5 are shorted within the DIP package.
Figure 2
Pin Configuration P-DSO-8-8(top view)
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Pin Configuration and Functionality 1.3 Pin Functionality
SoftS (Soft Start & Auto Restart Control) The SoftS pin combines the function of Soft Start in case of Start Up and Auto Restart Mode and the controlling of the Auto Restart Mode in case of error detection. Furthermore the blanking window for high load jumps is adjusted by means of the external capacitor connected to SoftS. FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWM-Comparator to control the duty cycle. The FBSignal controls in case of light load the Active Burst Mode of the controller. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the external PowerMOS. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode. Gate The Gate pin is the output of the internal driver stage connected to the Gate of an external PowerMOS. HV (High Voltage) The HV pin is connected to the rectified DC input voltage. It is the input for the integrated 500V Startup Cell. VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 8.5V and 21V. GND (Ground) The GND pin is the ground of the controller.
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2
Figure 3
Version 2.0
CBulk Snubber + Converter DC Output VOUT CVCC
85 ... 270 VAC
HV
6.5V Power Management
VCC Startup Cell
RSoftS Internal Bias Voltage Reference VCC
3.25k 6.5V
GND
SoftS
1V Undervoltage Lockout
15V 0.72 8.5V
T2
T3 Power-Down Reset PWM Section Oscillator
Duty Cycle max
Latched Off Mode Reset VVCC < 6V
T1
Representative Blockdiagram
1 G3 Latched Off Mode Soft Start C7 Gate Driver & G9 & G7 1 G8 FF1 S RQ Soft-Start Comparator
Clock
CSoftS
5k
VCC
4.4V Thermal Shutdown
Tj >140C
21V
C1
& G1 Spike Blanking 8.0us
Representative Blockdiagram
7
& G4 PWM Comparator C8 C11 & G5 C9 Vcsth Auto Restart Mode 0.3V Propagation-Delay Compensation C10 x3.7 PWM OP C12 & G10 10k 1pF D1 Spike Blanking 190ns 1.66V
S1
4.0V
C2
1
G2
Gate
5.4V
C3
6.5V
RFB
4.8V
C4
5k Active Burst Mode
0.85V
FB
& G6 & G11 Current Mode
4.0V
C5
CS
RSense
10pF
1.32V
C6
Leading Edge Blanking 220ns
0.257V
Control Unit
Current Limiting
Representative Blockdiagram
ICE3DS01/G
F3 ICE3DS01L/LG
15 May 2003
F3 ICE3DS01L/LG
Functional Description
3
Functional Description
SMPS. There is no need for an extra over sizing of the SMPS, e.g. the transformer or PowerMOS.
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.2
HV
Power Management
Startup Cell VCC
3.1
Introduction
The F3 is the further development of the F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage startup cell is integrated into the IC which is switched off once the Undervoltage Lockout on-threshold of 15V is exceeded. The external startup resistor is no longer necessary. Power losses are therefore reduced. This increases the efficiency under light load conditions dramatically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. A new Latched Off Mode is implemented into the IC in order to increase the robustness and safety of the system. Latched Off Mode is only entered if very dangerous conditions occur that damage the SMPS if not switched off immediately. A restart of the system can then only be done by disconnecting the AC line. Auto Restart Mode reduces the average power conversion to a minimum. In this mode malfunctions are covered that could lead to a destruction of the SMPS if no dramatically reduced power limitation is provided over time. Once the malfunction is removed normal operation is immediately started after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage that is required for wide range
Power Management Internal Bias Latched Off Mode Reset VVCC < 6V Power-Down Reset Undervoltage Lockout 15V 8.5V
Voltage Reference
6.5V
Auto Restart Mode
T1
Active Burst Mode
Latched Off Mode
SoftS
Figure 4 Power Management
The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. The VCC charge current that is provided by the Startup Cell from the HV pin is 1.05mA. When VVCC exceeds the on-threshold VCCon=15V the internal voltage reference and bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore also the power losses are switched off caused by the Startup Cell which is connected to the bus voltage (HV). To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the
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Functional Description
controller can only take place after Active Mode was entered and VVCC falls below 8.5V. The maximum current consumption before the controller is activated is about 170A. When VVCC falls below the off-threshold VCCoff=8.5V the internal reference is switched off and the Power Down reset let T1 discharging the soft-start capacitor CSoftS at pin SoftS. Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The internal Voltage Reference is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 300A. When Active Burst Mode is entered the internal Bias is switched off in order to reduce the current consumption below 1.1mA while keeping the Voltage Reference still active as this is necessary in this mode. In case Latched Off Mode is entered VCC needs to be lowered below 6V to reset the Latched Off Mode. This is done usually by disconnecting the SMPS from the AC line. capacitor CSofts in combination with the internal pull up resistor RSoftS determines the duty cycle until VSoftS exceeds 4V. In the beginning CSoftS is immediately charged up to approx. 1V by T2. Therefore the Soft Start Phase takes place between 1V and 4V. Above VSoftsS = 4V there is no longer duty cycle limitation DCmax is controlled by comparator C7 as comparator C2 blocks the gate G7 (see Figure 6).The maximum charge current in the very first phase when VSoftS is below 1V is limited to 1.9mA.
VSoftS
max. Startup Phase 5.4V 4V
1V max. Soft Start Phase
3.3
Startup Phase
6.5V 3.25k
DCmax
DC1 DC2
t
RSoftS
T2 T3 1V
SoftS
CSoftS Soft Start C7 Soft-Start Comparator & G7 C2 4V
t1
Figure 6 Startup Phase
t2 t
Gate Driver
0.85V x3.7 PWM OP CS
By means of this extra charge stage there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 4V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to VSoftS = 4V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal.
Figure 5
Soft Start
During the Startup Phase a Soft Start is provided. A signal VSoftS which is generated by the external
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Functional Description 3.4 PWM Section
0.72 Oscillator Duty Cycle max
VCC
PW Section M
PWM-Latch
1
Z1
Gate
Clock
Soft Start Comparator PWM Comparator Current Limiting Comparator C3
FF1 1 G8 S R Q Gate Driver & G9
Figure 8
Gate Driver
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the external Power Switch threshold. This is achieved by a slope control of the rising edge at the driver's output (see Figure 9).
Gate
Figure 7 PWM Section
VGate
ca. t = 130ns
3.4.1 Oscillator The oscillator generates a frequency fswitch = 110kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.72. 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM-Latch when initiating the external Power Switch conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator, the Current-Limit comparator or comparator C3. In case of resetting the driver is shut down immediately. 3.4.3 Gate Driver The Gate Driver is a fast totem pole gate drive which is designed to avoid cross conduction currents and which is equipped with a zener diode Z1 (see Figure 8) in order to improve the control of the Gate attached power transistors as well as to protect them against undesirable gate overvoltages. The Gate Driver is active low at voltages below the undervoltage lockout threshold VVCCoff.
CLoad = 1nF 5V
t
Figure 9 Gate Rising Slope Thus the leading switch on spike is minimized. When the external Power Switch is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage.
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Functional Description 3.5
PWM Latch FF1
Current Limiting
Latched Off Mode Current Limiting Spike Blanking 190ns Propagation-Delay Compensation Vcsth C10 PWM-OP & G10 C12 0.257V 1.66V C11
The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.257V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand. 3.5.1 Leading Edge Blanking
VSense
Vcsth
tLEB = 220ns
Leading Edge Blanking 220ns
t
Figure 11 Leading Edge Blanking Each time when the external Power Switch is switched on a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. To avoid a premature termination of the switching pulse this spike is blanked out with a time constant of tLEB = 220ns. During that time there can't be an accidentally switch off of the gate drive.
Active Burst Mode
10k D1
1pF
CS
Figure 10 Current Limiting There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the external Power Switch is sensed via an external sense resistor RSense . By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the Power Switch in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. A further comparator C11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the Latched Mode by the comparator C11 a spike blanking with 190ns is integrated in the output path of comparator C11.
3.5.2
Propagation Delay Compensation
In case of overcurrent detection the shut down of the external Power Switch is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current Ipeak which depends on the ratio of dI/dt of the peak current (see Figure 12).
S igna l2
I S en s e
I p e ak 2 I p e ak 1 I L im it I O ve rsh o ot2
S ig nal1 t P rop a g atio n D elay
I O v e rs ho o t1
t
Figure 12 Current Limiting The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit
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Functional Description
the overshoot dependency on dI/dt of the rising primary current. That means the propagation delay time between exceeding the current sense threshold Vcsth and the switch off of the external Power Switch is compensated over temperature within a wide range. Current Limiting is now possible in a very accurate way (see Figure 13). E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level Vcsth=1V. A current ramp of dI/dt = 0.4A/s, that means dVSense/dt = 0.8V/s, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 12%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 13).
with compensation without compensation
3.6
Control Unit
The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode are combined with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window an accidentally entering of the Active Burst Mode is avoided. Furthermore the overload detection can be deactivated for a certain time. 3.6.1 Adjustable Blanking Window
SoftS
6.5V 5k RSoftS
V
1,3 1,25 1,2
VSense
1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
4.4V 1 S1 G2 & G4
V
dVSense dt
s
C3 5.4V 4.8V C4 & G5 Auto Restart Mode
Figure 13
Overcurrent Shutdown
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 14). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
V OSC
m a x. D u ty C ycle
Active Burst Mode & G6 C6 1.32V Control Unit
o ff tim e
FB
t
V Sense V c s th
P ro p a ga tio n D e la y
Figure 15
Adjustable Blanking Window
S igna l1
Figure 14
S ignal2 t
Dynamic Voltage Threshold Vcsth
VSoftS is clamped at 4.4V by the closed switch S1 after the SMPS is settled. If overload occurs VFB is exceeding 4.8V. Auto Restart Mode can't be entered as the gate G5 is still blocked by the comparator C3. But after VFB has exceeded 4.8V the switch S1 is opened via the gate G2. The external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS. The comparator C3 releases the gates
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F3 ICE3DS01L/LG
Functional Description
G5 and G6 once VSofts has exceeded 5.4V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor CSoftS. The same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C6 when VFB is falling below 1.32V. Only after VSoftS has exceeded 5.4V and VFB is still below 1.32V Active Burst Mode is entered. Once Active Burst Mode is entered gate G4 is blocked to ensure that the blanking window is only active before entering the Active Burst Mode. 3.6.2 Active Burst Mode The controller provides Active Burst Mode for low load conditions at VOUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on VOUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply. The Active Burst Mode is located in the Control Unit. Figure 16 shows the related components. 3.6.2.1 Entering Active Burst Mode The FB signal is always observed by the comparator C6 if the voltage level falls below 1.32V. In that case the switch S1 is released which allows the capacitor CSoftS to be charged starting from the clamped voltage level at 4.4V in normal operating mode. The gate G11 is blocked before entering Active Burst Mode. If VSoftS exceeds 5.4V the comparator C3 releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor CSoftS. After entering Active Burst Mode a burst flag is set which blocks the gate G4 and the internal bias is switched off in order to reduce the current consumption of the IC down to ca. 1.1mA. In this Off State Phase the IC is no longer self supplied so that therefore CVCC has to provide the VCC current (see Figure 17). Furthermore gate G11 is then released to start the next burst cycle once 1.32V is again exceeded. It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 8.5V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at VOUT. 3.6.2.2 Working in Active Burst Mode After entering the Active Burst Mode the FB voltage rises as VOUT starts to decrease due to the inactive PWM section. Comparator C5 observes the FB signal if the voltage level 4V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.257V to reduce the conduction losses and to avoid audible noise. If the load at VOUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 1.32V. At this level C6 deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 1.32V and 4V (see figure 17). 3.6.2.3 Leaving Active Burst Mode The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 26% during Active Burst Mode a certain load jump is needed that FB can exceed 4.8V. At this time C4 resets the Active Burst Mode which also
SoftS
6.5V
5k
RSoftS
4.4V
Internal Bias
&
S1
G4
Current Limiting
&
C3
5.4V
G10
4.8V
C4
FB
4.0V
C5
& G6
Active Burst Mode
C6
1.32V
Control Unit
& G11
Figure 16
Active Burst Mode
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Functional Description
blocks C12 by the gate G10. Maximum current can now be provided to stabilize VOUT. 3.6.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode, the others enter Auto Restart Mode. The Latched Off Mode can only be reset if VCC is falling below 6V. Both modes prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the chosen protection modes.
VFB
4.80V 4.00V 1.32V
Entering Active Burst Mode
Leaving Active Burst Mode
VSoftS
Blanking Window
5.40V 4.40V
t
VCC Overvoltage Overtemperature
Latched Off Mode Latched Off Mode
Short Winding/Short Diode Latched Off Mode Overload Open Loop VCC Undervoltage
t
Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode
VCS
1.00V 0.257V
Short Optocoupler
3.6.3.1
Current limit level during Active Burst Mode
Latched Off Mode
CS
Latched Off Mode Reset VVCC < 6V
VVCC
t
C11
1.66V
Spike Blanking 190ns
1
G3
Latched Off Mode
8.5V
IVCC
7.2mA
VCC
t
21V
C1
& G1
Spike Blanking 8.0us
4.8V
1.1mA
C4
Thermal Shutdown
Voltage Reference
VOUT
Max. Ripple < 1%
t
Tj >140C
Control Unit
FB
Figure 18
t
Latched Off Mode
Figure 17
Signals in Active Burst Mode
The VCC voltage is observed by comparator C1 if 21V is exceeded. The output of C1 is combined with the output of C4 which observes FB signal if 4.8V is
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F3 ICE3DS01L/LG
Functional Description
exceeded. Therefore the overvoltage detection is only activated if the FB signal is outside the operating range > 4.8V, e.g. when Open Loop happens. Therewith small voltage overshoots of VVCC during normal operating can not start the Latched Off Mode. The internal Voltage Reference is switched off once Latched Off Mode is entered in order to reduce the current consumption of the IC as much as possible. Latched Off Mode can only be reset by decreasing VVCC < 6V. In this stage only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/ VVCCoff. In this phase the average current consumption is only 300A. As there is no longer a self supply by the auxiliary winding VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 8.5V. The Startup Cell is switched off again when VCC has exceeded 15V. As the Latched Off Mode was entered there is no Start Up Phase after VCC has exceeded the switch-on level of the Undervoltage Lockout. Therefore VCC changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 19). short winding or short diode C10 is no longer able to limit the CS signal at 1V. C11 detects then the over current and enters immediately the Latched Off Mode to keep the SMPS in a safe stage. 3.6.3.2 Auto Restart Mode
SoftS
6.5V 5k RSoftS
4.4V 1 S1 G2 Voltage Reference C3 5.4V 4.8V C4 & G5 Auto Restart Mode Control Unit
VVCC
15V
FB
8.5V
IVCCStart
1.05mA
Figure 20
t
Auto Restart Mode
VOUT
Figure 19 Signals in Latched Off Mode
t
After detecting a junction temperature higher than 140C Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0s to ensure system reliability. Furthermore short winding and short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal operating mode comparator C10 keeps the maximum level of the CS signal at 1V. If there is a failure such as
In case of Overload or Open Loop FB exceeds 4.8V which will be observed by C4. At this time S1 is released that VSoftS can increase. If VSoftS exceeds 5.4V which is observed by C3 Auto Restart Mode is entered as both inputs of the gate G5 are high. In combining the FB and SoftS signals there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. This time window is the same as for the Active Burst Mode and can therefore be adjusted by the external CSoftS. In case of VCC undervoltage the UVLO starts a new startup cycle. Short Optocoupler leads to VCC undervoltage as there is now self supply after activating the internal reference and bias. In contrast to the Latched Off Mode there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase the conditions are again checked whether the failure is still present. Normal operation is proceeded once the failure mode is removed that leads to Auto Restart Mode.
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Symbol Limit Values min. max. 500V 22 6.5 6.5 22 6.5 150 150 0.45 0.90 185 90 3 V V V V V V C C W W K/W K/W kV P-DSO-8-8, Tamb < 50C P-DIP-8-6, Tamb < 50C P-DSO-8-8 P-DIP-8-6 Human body model1) Internally clamped at 11.5V Unit Remarks
Parameter
HV Voltage VCC Supply Voltage FB Voltage SoftS Voltage Gate Voltage CS Voltage Junction Temperature Storage Temperature Total Power Dissipation
VHV VVCC VFB VSoftS VGate VCS Tj TS PtotDSO8 PtotDIP8
-0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 -
Thermal Resistance Junction-Ambient ESD Capability (incl. Pin HV)
1)
RthJADSO8 RthJADIP8 VESD
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol Limit Values min. max. 20 130 V C Max value limited due to thermal shut down of controller Unit Remarks
Parameter
VCC Supply Voltage Junction Temperature of Controller
VVCC TjCon
VVCCoff -25
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F3 ICE3DS01L/LG
Electrical Characteristics 4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range TJ from - 25 C to 130 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed. Symbol min. Limit Values typ. 170 -1.05 -0.88 2 6.0 7.2 300 300 max. 220 -0.55 20 7.5 8.7 A mA mA A mA mA A A VSoftS = 4.4V IFB = 0 IFB = 0 ISofts = 0 IFB = 0 ISofts = 0 VFB = 2.5V VSoftS = 4.4V VVCC = 9V VFB = 2.5V VSoftS = 4.4V VVCC =14V VVCC = 0V VVCC =14V VVCC>16V Unit Test Condition
Parameter
Start Up Current VCC Charge Current
IVCCstart IVCCcharge1 IVCCcharge2 IStartLeak IVCCsup1
-1.60 -
Start Up Cell Leakage Current Supply Current with Inactive Gate
Supply Current with Active Gate IVCCsup2 (CLoad=1nF) Supply Current in Latched Off Mode Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate IVCClatch IVCCrestart
IVCCburst1 IVCCburst2
-
1.1 1.0
1.3 1.2
mA mA
VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis 4.3.2
VVCCon VVCCoff VVCChys
14.2 8.0 -
15.0 8.5 6.5
15.8 9.0 -
V V V
Internal Voltage Reference Symbol min. Limit Values typ. 6.50 max. 6.63 V measured at pin FB IFB = 0 Unit Test Condition
Parameter
Trimmed Reference Voltage
VREF
6.37
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Electrical Characteristics
4.3.3 Parameter PWM Section Symbol min. Fixed Oscillator Frequency fOSC1 fOSC2 Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Max. Level of Voltage Ramp Dmax Dmin AV VMax-Ramp 98 102 0.67 0 3.5 0.3 16 39 Limit Values typ. 110 110 0.72 3.7 0.85 0.7 20 50 max. 119 117 0.77 3.9 4.75 27 62 V V V k k CS=1V limited by Comparator C41) VFB < 0.3V kHz kHz Tj = 25C Unit Test Condition
VFB Operating Range Min Level VFBmin VFB Operating Range Max level VFBmax Feedback Pull-Up Resistor Soft-Start Pull-Up Resistor
1)
RFB RSoftS
Design characteristic (not meant for production testing) Control Unit Symbol min. Limit Values typ. 4.00 4.40 5.40 1.9 1.32 4.00 4.80 max. 4.15 4.57 5.60 1.40 4.15 4.98 V V V mA V V V VFB > 5V VFB < 4.5V VFB > 5V VSoftS = 0V VSoftS > 5.6V After Active Burst Mode is entered VSoftS > 5.6V Unit Test Condition
4.3.4 Parameter
Deactivation Level for SoftS Comparator C7 by C2 Clamped VSoftS Voltage during Normal Operating Mode Activation Limit of Comparator C3 SoftS Startup Current Active Burst Mode Level for Comparator C6 Active Burst Mode Level for Comparator C5 Over Load & Open Loop Detection Limit for Comparator C4 Overvoltage Detection Limit Latched Thermal Shutdown Spike Blanking Power Down Reset for Latched Mode Note:
VSoftSC2 VSoftSclmp VSoftSC3 ISoftSstart VFBC6 VFBC5 VFBC4
3.85 4.23 5.20 1.23 3.85 4.62
VVCCOVP TjSD tSpike VVCCPD
20 130 4.0
21 140 8.0 6.0
22 150 7.5
V C s V
VFB > 5V guaranteed by design
After Latched Off Mode is entered
The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD
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Electrical Characteristics
4.3.5 Parameter Current Limiting Symbol min. Peak Current Limitation (incl. Propagation Delay Time) (see Figure 7) Over Current Detection for Latched Off Mode Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Spike Blanking for Comparator C11 CS Input Bias Current 4.3.6 Parameter Driver Section Symbol min. GATE Low Voltage VGATElow -0.2 GATE High Voltage VGATEhigh GATE Rise Time (incl. Gate Rising Slope) GATE Fall Time GATE Current, Peak, Rising Edge GATE Current, Peak, Falling Edge
1) 2)
Limit Values typ. 1.000 max. 1.050
Unit
Test Condition
Vcsth
0.950
V
dVsense / dt = 0.6V/s
VCS1 VCS2 tLEB tCSspike ICSbias
1.570 0.232 -1.0
1.66 0.257 220 190 -0.2
1.764 0.282 0
V V ns ns A VCS =0V VFB < 1.2V VSoftS = 4.4V
Limit Values typ. 0.8 1.6 0.2 11.5 10.5 7.5 150 55 max. 1.2 1.5 2.0 0.7
Unit
Test Condition
V V V V V V V V ns ns A A
VVCC = 5 V IGate = 5 mA VVCC = 5 V IGate = 20 mA IGate = 0 A IGate = 20 mA IGate = -20 mA VVCC = 20V CL = 4.7nF VVCC = 11V CL = 4.7nF VVCC = VVCCoff + 0.2V CL = 4.7nF VGate = 2V ...9V1) CL = 4.7nF VGate = 9V ...2V1) CL = 4.7nF CL = 4.7nF2) CL = 4.7nF2)
trise tfall IGATE IGATE
-0.5 -
Transient reference value Design characteristic (not meant for production testing)
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F3 ICE3DS01L/LG
Typical Performance Characteristics
5
190 186
Typical Performance Characteristics
8,0 7,5
Start Up Current I VCCstart [uA]
182 178 174
PI-001
VCC Supply Current IVCCsup1 [mA]
7,0 6,5 6,0
PI-004
170 166 162 158 154 150
5,5 5,0 4,5 4,0 3,5 3,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 21
1,5 1,4 1,3 1,2 1,1
Start Up Current IVCCstart
Figure 24
9,0 8,5
VCC Supply Current IVCCsup1
VCC Charge Current IVCCcharge1 [mA]
VCC Supply Current IVCCsup2 [mA]
8,0 7,5 7,0
PI-005
0,9 0,8 0,7 0,6 0,5
PI-002
1,0
6,5 6,0 5,5 5,0 4,5 4,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 22
1,5 1,4 1,3 1,2 1,1
VCC Charge Current IVCCcharge1
Figure 25
400 380
VCC Supply Current IVCCsup2
VCC Charge Current I VCCcharge2 [mA]
VCC Supply Current IVCClatch [uA]
360 340 320
PI-006
PI-003
1,0 0,9 0,8 0,7 0,6 0,5
300 280 260 240 220 200
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 23
VCC Charge Current IVCCcharge2
Figure 26
VCC Supply Current IVCClatch
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F3 ICE3DS01L/LG
Typical Performance Characteristics
400 380
16,0 15,8
VCC Turn-On Threshold VVCCon [V]
VCC Supply Current IVCCrestart [uA]
360 340 320
PI-007
15,6 15,4 15,2
PI-010
300 280 260 240 220 200
15,0 14,8 14,6 14,4 14,2 14,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 27
1,20 1,17
VCC Supply Current IVCCrestart
Figure 30
9,0 8,9
VCC Turn-On Threshold VVCCon
VCC Turn-Off Threshold VVCCoff [V]
VCC Supply Current IVCCburst1 [mA]
1,14 1,11 1,08
PI-008
8,8 8,7 8,6
PI-011
1,05 1,02 0,99 0,96 0,93 0,90
8,5 8,4 8,3 8,2 8,1 8,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 28
1,20
VCC Supply Current IVCCburst1
Figure 31
7,0
VCC Turn-Off Threshold VVCCoff
VCC Turn-On/Off Hysteresis VVCChys [V]
1,17
6,9 6,8 6,7 6,6
PI-012
VCC Supply Current IVCCburst2 [mA]
1,14 1,11 1,08
PI-009
1,05 1,02 0,99 0,96 0,93 0,90
6,5 6,4 6,3 6,2 6,1 6,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 29
VCC Supply Current IVCCburst2
Figure 32
VCC Turn-On/Off Hysteresis VVCChys
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F3 ICE3DS01L/LG
Typical Performance Characteristics
6,60 6,58 6,56 6,54
3,90 3,86 3,82 3,78
Reference Voltage VREF [V]
PWM-OP Gain AV
6,52
PI-013
3,74
PI-016
6,50 6,48 6,46 6,44 6,42 6,40
3,70 3,66 3,62 3,58 3,54 3,50
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 33
120
Reference Voltage VREF
Figure 36
1,10
PWM-OP Gain AV
Max. Level Voltage Ramp VMax-Ramp [V]
118
1,05 1,00 0,95 0,90
PI-017
Oscillator Frequency fOSC1 [kHz]
116 114 112
PI-014
110 108 106 104 102 100
0,85 0,80 0,75 0,70 0,65 0,60
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 34
0,750
Oscillator Frequency fOSC1
Figure 37
26
Max. Level Voltage Ramp VMax-Ramp
0,740 0,735
Feedback Pull-Up Resistor RFB [kOhm]
0,745
25 24 23 22
PI-018
Max. Duty Cycle
0,730
PI-015
0,725 0,720 0,715 0,710 0,705 0,700
21 20 19 18 17 16
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 35
Max. Duty Cycle Dmax
Figure 38
Feedback Pull-Up Resistor RFB
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Typical Performance Characteristics
60
5,65
Soft-Start Pull-Up Resistor RSoftS [kOhm]
56 54 52
PI-019
Threshold Comparator C3 V SoftSC3 [V]
58
5,60 5,55 5,50 5,45
PI-022
50 48 46 44 42 40
5,40 5,35 5,30 5,25 5,20 5,15
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 39
4,20 4,16 4,12 4,08 4,04
Soft-Start Pull-Up Resistor RSoftS
Figure 42
1,360 1,352
Threshold Comparator C3 VSoftSC3
Threshold Comparator C2 VSoftSC2 [V]
Threshold Comparator C6 VFBC6 [V]
1,344 1,336 1,328
PI-023
3,96 3,92 3,88 3,84 3,80
PI-020
4,00
1,320 1,312 1,304 1,296 1,288 1,280
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 40
4,60 4,56
Threshold Comparator C2 VSoftSC2
Figure 43
4,20 4,16
Threshold Comparator C6 VFBC6
Clamped SoftS Voltage V SoftSclmp [V]
Threshold Comparator C5 VFBC5 [V]
4,52 4,48 4,44
PI-021
4,12 4,08 4,04
PI-024
4,40 4,36 4,32 4,28 4,24 4,20
4,00 3,96 3,92 3,88 3,84 3,80
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 41
Clamped SoftS Voltage VSoftSclmp
Figure 44
Threshold Comparator C5 VFBC5
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Typical Performance Characteristics
5,00 4,96
1,05
Peak Current Limitation Vcsth [V]
Threshold Comparator C4 VFBC4 [V]
1,04 1,03 1,02 1,01
PI-028
4,92 4,88 4,84
PI-025
4,80 4,76 4,72 4,68 4,64 4,60
1,00 0,99 0,98 0,97 0,96 0,95
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 45
22,0
Threshold Comparator C4 VFBC4
Figure 48
1,700 1,688
Peak Current Limitation Vcsth
Overvoltage Detection Limit VVCCOVP [V]
21,8 21,6 21,4 21,2
PI-026
Over Current Detection VCS1 [V]
1,676 1,664 1,652
PI-029
21,0 20,8 20,6 20,4 20,2 20,0
1,640 1,628 1,616 1,604 1,592 1,580
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 46
8,0 7,6
Overvoltage Detection Limit VVCCOVP
Figure 49
0,270 0,267
Over Current Detection VCS1
VCC Power Down Reset VVCCPD [V]
Peak Current Limitation VCS2 [V]
7,2 6,8 6,4
PI-027
0,264 0,261 0,258
PI-030
6,0 5,6 5,2 4,8 4,4 4,0
0,255 0,252 0,249 0,246 0,243 0,240
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 47
Threshold Power Down Reset VVCCPD
Figure 50
Peak Current Limitation VCS2
Version 2.0
24
15 May 2003
F3 ICE3DS01L/LG
Typical Performance Characteristics
400 370
12,0 11,7
Leading Edge Blanking tLEB [ns]
Gate High Voltage VGATEhigh [V]
340 310 280
PI-031
11,4 11,1 10,8
PI-034
250 220 190 160 130 100
10,5 10,2 9,9 9,6 9,3 9,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 51
300
Leading Edge Blanking tLEB
Figure 54
300 280 260
GATE High Voltage VGATEhigh
CS Spike Blanking for C11 tCSspike [ns]
280 260
Gate Rise Time trise [ns]
240 220
PI-032
240 220
PI-035
200 180 160 140 120 100
200 180 160 140 120 100
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 52
1,3 1,2
CS Spike Blanking for C11 tCSspike
Figure 55
80 76 72
GATE Rise Time trise
GATE Low Voltage VGATElow [V]
1,1
GATE Fall Time tfall [ns]
1,0 0,9
PI-033
68 64
PI-036
0,8 0,7 0,6 0,5 0,4 0,3
60 56 52 48 44 40
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125
Junction Temperature [C]
Junction Temperature [C]
Figure 53
GATE Low Voltage VGATElow
Figure 56
GATE Fall Time tfall
Version 2.0
25
15 May 2003
F3 ICE3DS01L/LG
Outline Dimension
6
Outline Dimension
P-DIP-8-6 (Plastic Dual In-Line Outline)
Figure 57
P-DSO-8-8 (Plastic Dual Small Outline)
Figure 58
Dimensions in mm
Version 2.0
26
15 May 2003
Total Quality Management
Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Wir werden Sie uberzeugen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced.
http://www.infineon.com
Published by Infineon Technologies AG

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